Semiconductor chip package

ABSTRACT

A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No.2007-56852 filed on Jun. 11, 2007, in the Korean Intellectual PropertyOffice, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor chip package forpackaging a semiconductor chip.

2. Description of the Related Art

In the electronics market, demands for portable systems are drasticallyincreasing. To meet such increasing demands, slim and lightweightcomponents must be mounted in those systems.

To realize such slim and lightweight components, there are needs for atechnique for reducing a size of individual devices, a system-on-chip(SOC) technique for integrating a plurality of individual devices intoone chip, and a system-in-package (SIP) technique for integrating aplurality of devices into one package.

FIG. 1A is a cross-sectional view illustrating an example of a relatedart semiconductor chip package. Referring to FIG. 1A, a related artsemiconductor chip package 10 includes at least one chip 12 flip-chipbonded onto a substrate 11 by using a plurality of bump balls 13, and ametal can 15 formed of a metallic material on the substrate 11. Themetal can 15 protects the chip 12 and a passive component from theexternal environment. Also, the metal can 15 prevents high-frequencysignals generating during chip operation from affecting an adjacentpackage, or blocks external harmful electromagnetic waves.

FIG. 1B is a cross-sectional view illustrating another example of arelated art semiconductor chip package. Referring to FIG. 1B, a relatedart semiconductor chip package 20 includes at least one chip 22wire-bonded onto a substrate 21 by using a plurality of metal wires 23,and a metal can 25 formed of a metallic material on the substrate 21.The metal can 25 protects the chip 22 and a passive component 24 fromthe external environment. Also, the metal can 25 prevents high-frequencysignals generating during chip operation from affecting an adjacentpackage, or blocks external harmful electromagnetic waves.

Undescribed reference numerals 16 and 26 in FIGS. 1A and 1B indicatemain boards on which the semiconductor chip packages 10 and 20 aremounted, respectively.

In the related art semiconductor chip packages 10 and 20, the passivecomponents 14 and 24 such as a resistor, a capacitor and a coil aremounted on the substrates 11 and 21 besides the chips 12 and 22, and themetal cans 15 and 25 are also mounted on the substrates 11 and 21 toshield the chips 11 and 22 and the passive component 14 and 24 from theexternal environment. For this reason, the related art semiconductorchip packages 10 and 20 have limitations in that assembly processes ofthe semiconductor chips 10 and 20 are complicated and take long time tocomplete, lowering operational productivity. Also, miniaturization ofthe semiconductor chip packages 10 and 20 is limited because of themetal cans 15 and 25.

Also, the substrates 11 and 21 must include separate ground lines (notshown) electrically connected with ground terminals of the chips 12 and22, and separate ground lines (not shown) electrically connected withthe metal cans 15 and 25 mounted thereon. Hence, the substrate structureis complicated, increasing manufacturing costs.

SUMMARY OF THE INVENTION

An aspect of the present invention provides a semiconductor chippackage, which can simplify a package manufacturing process, reduce thenumber of components to lower the manufacturing costs, reduce a packagevolume to contribute miniaturization of a package, and improve groundperformance.

According to an aspect of the present invention, there is provided asemiconductor chip package including: a main board; a ceramic substratehaving a cavity within which at least one chip is electrically mounted,the cavity being placed at a lower portion of the ceramic substratefacing the main board; and a conductive shielding layer provided with apredetermined thickness on the outside of the ceramic substrate, whereinthe ceramic substrate includes: at least one first ground lineelectrically connecting the conductive shielding layer with the mainboard; at least one second ground line electrically connecting theconductive shielding layer with the chip; and at least one signal lineelectrically connecting the chip with the main board.

The conductive shielding layer may cover a top surface and outer sidesurfaces of the ceramic substrate.

The conductive shielding layer may include bar-shaped patternsalternately disposed on a top surface of the ceramic substrate.

The conductive shielding layer may include a helical pattern on a topsurface of the ceramic substrate.

The first ground line may include a first conductive via penetrating theceramic substrate and electrically connecting the conductive shieldinglayer with a ground terminal of the main board.

The second ground line may include a second conductive via penetratingthe ceramic substrate and electrically connecting the conductiveshielding layer with a ground terminal of the chip.

The signal line may include: an inner pattern provided in the ceramicsubstrate and electrically connected with a signal terminal of the chip;and a signal via formed in the ceramic substrate and electricallyconnecting the inner pattern with a signal terminal of the main board.

The cavity may be filled with a resin filler covering and protecting thechip.

The chip may be mounted to the ceramic substrate by flip-chip bonding.

The chip may be mounted to the ceramic substrate by wire-bonding.

According to another aspect of the present invention, there is provideda semiconductor chip package including: a main board; a ceramicsubstrate having a cavity within which at least one chip is electricallymounted, the cavity being placed at a lower portion of the ceramicsubstrate facing the main board; and a shielding substrate stacked onthe ceramic substrate and including a shielding layer, wherein theceramic substrate includes: at least one third ground line electricallyconnecting the shielding layer of the shielding substrate with the mainboard; at least one fourth ground line electrically connecting theshielding layer of the shielding substrate with the chip; and at leastone signal line electrically connecting the chip with the main board.

The shielding layer may include: an upper conductive shielding layerprovided at an upper portion of the shielding substrate; a lowerconductive shielding layer provided at a lower portion of the shieldingsubstrate; and an intermediate conductive shielding layer disposedbetween the upper conductive shielding layer and the lower conductiveshielding layer.

The upper conductive shielding layer and the intermediate conductiveshielding layer may be connected through a conductive via, and the upperconductive shielding layer and the lower conductive shielding layer maybe connected through another conductive via.

The upper conductive shielding layer may cover the ceramic substrate.

The upper conductive shielding layer may include bar-shaped patternsalternately disposed on the ceramic substrate.

The upper conductive shielding layer may include a helical patterndisposed on the ceramic substrate.

The third ground line may include a third conductive via penetrating theceramic substrate and electrically connecting the shielding layer with aground terminal of the main board.

The fourth ground line may include a fourth conductive via penetratingthe ceramic substrate and electrically connecting the shielding layerwith a ground terminal of the chip.

The signal line may include: an inner pattern provided in the ceramicsubstrate and electrically connected with a signal terminal of the chip;and a signal via formed in the ceramic substrate and electricallyconnecting the inner pattern with a signal terminal of the main board.

The cavity may be filled with a resin filler covering and protecting thechip.

The chip may be mounted to the ceramic substrate by flip-chip bonding.

The chip may be mounted to the ceramic substrate by wire-bonding.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIGS. 1A and 1B are cross-sectional views of related art semiconductorchip packages, respectively illustrating a semiconductor chip packageincluding a chip mounted by a flip-chip method, and a semiconductor chippackage including a chip mounted by a wire-bonding method;

FIGS. 2A and 2B are cross-sectional views of semiconductor chip packagesaccording to an embodiment of the present invention, respectivelyillustrating a semiconductor chip package including a chip mounted by aflip-chip method and a semiconductor chip package including a chipmounted by a wire-bonding method;

FIGS. 3A and 3B are views of conductive shielding layers used in thesemiconductor chip packages of FIGS. 2A and 2B, respectively provided inthe form of bar-shaped patterns and a helical pattern.

FIGS. 4A and 4B are cross-sectional views of semiconductor chip packagesaccording to another embodiment of the present invention, respectivelyillustrating a semiconductor chip package including a chip mounted by aflip-chip method and a semiconductor chip package including a chipmounted by a wire-bonding method; and

FIG. 5 is a cross-sectional view of a shielding substrate used in thesemiconductor chip packages of FIGS. 4A and 4B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Exemplary embodiments of the present invention will now be described indetail with reference to the accompanying drawings.

FIGS. 2A and 2B are cross-sectional views of semiconductor chip packagesaccording to an embodiment of the present invention. FIG. 2A illustratesa semiconductor chip package in which a chip is mounted by a flip-chipmethod, and FIG. 2B illustrates a semiconductor chip package in which achip is mounted by a wire-bonding method.

The semiconductor chip package 100 according to the embodiment of thepresent invention includes a main board 101, a ceramic substrate 110 anda conductive shielding layer 120.

The main board 101 is a main substrate on which the ceramic substrate110 is mounted by a land grid array (LGA) method or a ball grid array(BGA) method using a plurality of solder balls as a medium, and aplurality of passive components 105 are mounted.

The ceramic substrate 110 has a cavity 111 with a predetermined size,which is open at one side facing the main board 101. The ceramicsubstrate 110 may have a stack structure of ceramic sheets that arestacked forming the cavity 111 therein.

At least one chip 112 is electrically mounted within the cavity 111.Referring to FIG. 2A, the chip 112 is mounted within the cavity 111 by aflip-chip bonding method such that a plurality of terminals provided onan active surface of the chip 112 are electrically connected with aplurality of pads 113 provided on a closed side of the cavity 111 byusing bump balls 114 placed on the pads 113. Referring to FIG. 2B, thechip 112 is mounted by a wire-bonding method such that the plurality ofterminals provided on the active surface of the chip 112 areelectrically connected to the plurality of pads 113 provided on theclosed side of the cavity 111 by using a plurality of metal wires 114 a.

According to a set device employing the semiconductor chip package 100,the chip 112 may be one of a memory chip such as a static random accessmemory (SRAM) and a dynamic random access memory (DRAM), a digitalintegrated circuit chip, a radio frequency (RF) integrated circuit chip,and a baseband chip.

The cavity 111 is filled with a resin filler 116 to protect the chip 112mounted by the flip-chip bonding method or the wire bonding method fromthe external environment.

The chip 112 mounted within the cavity 111 is disposed in a closed spaceformed between the main board 101 and the ceramic substrate 110, therebyminimizing signal propagation from the chip 112 to the outside.

The ceramic substrate 110 may be a low temperature co-fired ceramic(LTCC) substrate provided by an LTCC technique. In the LTCC technique,passive components for realizing a given circuit, such as resistors,inductors, capacitors, filters, baluns and couplers are realized in aplurality of glass-ceramic-based green sheets by using a photopatterning process and a screen printing process using a highlyconductive material such as Ag and Cu, then the green sheets arestacked, and a stack structure thereof is co-fired below 1000° C.

Also, the conductive shielding layer 120 is a shielding member of ahighly conductive metal, which is provided with a predetermine thicknesson the outside of the ceramic substrate 110.

The conductive shielding layer 120 may cover the entire top surface andouter side surfaces of the ceramic substrate 110 as illustrated in FIGS.2A and 2B. However, the present invention is not limited thereto. Asshown in FIGS. 3A and 3B, the conductive shielding layer 120 may beimplemented in the form of bar-shaped patterns 120 a alternatelydisposed on the top surface of the ceramic substrate 110, or in the formof a helical pattern 120 b provided on the top surface of the ceramicsubstrate 110.

The ceramic substrate 110 includes at least one first ground line 121electrically connecting the conductive shielding layer 120 with the mainboard 101. The first ground line 121 may also be referred to as a firstconductive via. The first ground line 121, i.e., the first conductivevia, includes a first via hole 121 a vertically penetrating the ceramicsubstrate 110, and a conductive material 121 b provided in the first viahole 121 a and electrically connecting the conductive shielding layer120 with a ground terminal among a plurality of terminals provided on atop surface of the main board 101.

The ceramic substrate 110 includes at least one second ground line 122to electrically connect the conductive shielding layer 120 with the chip112. The second ground line 122 may also be referred to as a secondconductive via. The second ground line 122, i.e., the second conductivevia, includes a second via hole 122 a vertically penetrating the ceramicsubstrate 110 corresponding to the cavity 111 within which the chip 112is mounted, and a conductive material 122 b provided in the second viahole 122 a and electrically connecting the conductive shielding layer120 with a ground terminal among the plurality of terminals provided onthe active surface of the chip 112.

The ceramic substrate 110 includes at least one signal line 129electrically connecting the chip 112 with the main board 101. The signalline 129 includes an inner pattern 129 a and a signal via 129 b. Theinner pattern 129 a is provided in the ceramic substrate 110 andelectrically connected with a signal terminal among the plurality ofterminals provided on the active surface of the chip 112. The signal via129 b includes a signal via hole vertically penetrating the ceramicsubstrate 110, and a conductive material filled in the signal via holeand electrically connecting the inner pattern 129 a with a signalterminal among the plurality of terminals provided on the main board101.

FIGS. 4A and 4B are cross-sectional views of semiconductor chip packagesaccording to another embodiment of the present invention. FIG. 4Aillustrates a semiconductor chip package in which a chip is mounted by aflip-chip method, and FIG. 4B illustrates a semiconductor chip packagein which a chip is mounted by a wire-bonding method.

A semiconductor chip package 200 according to another embodiment of thepresent invention includes a main board 201, a ceramic substrate 210 anda shielding substrate 220.

As in the embodiment of FIGS. 2A and 2B, the main board 201 according tothe current embodiment is a main substrate on which the ceramicsubstrate 210 is mounted by a BGA or LGA method.

As in the embodiment of FIGS. 2A and 2B, the ceramic substrate 210 has acavity 211 which has a predetermined size and is open at one side facingthe main board 201. The ceramic substrate 210 is a substrate memberhaving a stack structure of ceramic sheets that are stacked forming thecavity 211.

At least one chip 212 is mounted within the cavity 211. Referring toFIG. 4A, the chip 212 is mounted within the cavity 211 by a flip-chipbonding method such that a plurality of terminals provided on an activesurface of the chip 212 are electrically connected with a plurality ofpads 213 provided on a closed side of the cavity 211 by using bump balls214 placed on the pads 213. Referring to FIG. 4B, the chip 212 ismounted within the cavity 211 by a wire-bonding method such that theplurality of terminals provided on the active surface of the chip 212are electrically connected with the plurality of pads 213 on the closedside of the cavity 211 by using a plurality of metal wires 214 a.

The cavity 211 is filled with a resin filler 216 to protect the chip 212mounted by the flip-chip bonding method or the wire-bonding method.

The chip 212 mounted within the cavity 211 is disposed in a closed spacebetween the main board 201 and the ceramic substrate 210. Thus, signalpropagation from the chip 212 to the outside is minimized.

The shielding substrate 220 may be a substrate member integrally stackedon a top surface of the ceramic substrate 210.

As illustrated in FIG. 5, the shielding substrate 220 is a ceramicsubstrate having a stack structure of a plurality of ceramic sheets andincluding a shielding part 221. The shielding part 221 of the shieldingsubstrate 220 includes an upper conductive shielding layer 221 c, alower conductive shielding layer 221 a, and an intermediate conductiveshielding layer 221 b. The upper conductive shielding layer 221 cincludes an electrode formed by printing an electrode pattern on theuppermost ceramic sheet, and is disposed at an upper portion of theshielding substrate 220. The lower conductive shielding layer 221 aincludes an electrode formed by printing an electrode pattern on thelowermost ceramic sheet, and is disposed at a lower portion of theshielding substrate 220. The intermediate conductive shielding layer 221b includes an electrode formed by printing an electrode pattern on anintermediate ceramic sheet therebetween.

The upper conductive shielding layer 221 c is connected with theintermediate conductive shielding layer 221 b through at least oneconductive via 222 a. The upper conductive shielding layer 221 c isconnected with the lower conductive shielding layer 221 a throughanother conductive via 222 b.

The upper conductive shielding layer 221 c provided at the upper portionof the shielding substrate 220 may cover the entire top surface of theshielding substrate 220. However, the present invention is not limitedthereto. Like the conductive shielding layer 120 of FIGS. 3A and 3B, theupper conductive shielding layer 221 c may be realized as bar-shapedpatterns alternately disposed on the top surface of the shieldingsubstrate 220, or as a helical pattern on the top surface of theshielding substrate 220.

The ceramic substrate 210 on which the shielding substrate 220 isstacked includes at least one third ground line 223 electricallyconnecting the shielding part 221 with the main board 201. The thirdground line 223 may also be referred to as a third conductive via. Thethird ground line 223, i.e., the third conductive via, includes a thirdvia hole 223 a vertically penetrating the ceramic substrate 210 and aconductive material 223 b provided in the third via hole 223 a andelectrically connecting a ground terminal among a plurality of terminalsprovided on a top surface of the main board 201 with the lowerconductive shielding layer 221 a of the shielding part 221.

The ceramic substrate 210 includes at least one fourth ground line 224to electrically connect the shielding part 221 with the chip 212. Thefourth ground line 224 may also be referred to as a fourth conductivevia. The fourth ground line 224, i.e., the fourth conductive via,includes a fourth via hole 224 a vertically penetrating the ceramicsubstrate 212 corresponding to the cavity 211 within which the chip 212is mounted, and a conductive material 224 b provided in the fourth viahole 224 a and electrically connecting the lower conductive shieldinglayer 221 a of the shielding part 221 with a ground terminal among theplurality of terminals provided on the active surface of the chip 212.

The ceramic substrate 210 includes at least one signal line 229electrically connecting the chip 212 with the main board 201. The signalline 229 includes an inner pattern 229 a and a signal via 229 b. Theinner pattern 229 a is provided in the ceramic substrate 210 to beelectrically connected with a signal terminal among the plurality ofterminals provided on the active surface of the chip 212. The signal via229 b includes a signal via and a conductive material filling the signalvia, and electrically connects the inner pattern 229 a with a signalterminal of a plurality of terminal provided on the main board 201.

The ceramic substrate 210 and the shielding substrate 220 may be a lowtemperature co-fired ceramic (LTCC) substrate provided by an LTCCtechnique. In the LTCC technique, passive components for realizing agiven circuit, such as resistors, inductors, capacitors, filters, balunsand couplers are realized in a plurality of glass-ceramic-based greensheets by using a photo patterning process and a screen printing processusing a highly conductive material such as Ag and Cu, then the greensheets are stacked, and a stack structure thereof is co-fired below1000° C.

Accordingly, the passive components to be mounted on the main board 101,such as the capacitors, the resistors and the inductors, can be mountedin the form of patterns in the ceramic substrate 210 and the shieldingsubstrate 220.

Electromagnetic signals are generated from the chips 112 and 212provided in the semiconductor chip packages 100 and 200. However,according to the embodiment of FIGS. 2A and 2B, the electromagneticsignals are transmitted to the ground terminal of the main board 101through the first and second ground lines 121 and 122 provided in theceramic substrate 110. Also, according to the embodiment of FIGS. 4A and4B, the electromagnetic signals are transmitted to the ground terminalof the main board 201 through the third and fourth ground lines 223 and224 provided in the ceramic substrate 210 according to the embodiment ofFIGS. 4A and 4B.

The chip 112 of FIGS. 2A and 2B is disposed in a closed space betweenthe ceramic substrate 110 and the main board 101, and the chip 212 ofFIGS. 4A and 4B is also disposed in a closed space between the ceramicsubstrate 210 and the main board 201, thereby minimizing the influenceof harmful electromagnetic waves to adjacent electronic components.

Accordingly, the harmful electromagnetic signals generated from thechips 112 and 212 are prevented from undesirably affecting otheradjacent electronic components and thus causing deterioration of acircuit function and defective operations of a device.

According to the embodiment of FIGS. 2A and 2B, harmful electromagneticsignals generated from the outside are transmitted into the groundterminal of the main boards 101 through the conductive shielding layer120 provided on the ceramic substrate 110, and the first ground line 121provided in the ceramic substrate 110. According to the embodiment ofthe FIGS. 4A and 4B, the harmful electromagnetic signals generated fromthe outside are transmitted to the ground terminal of the main board 201through the shielding part 221 on the ceramic substrate 210, and thethird ground line 223 in the ceramic substrate 210.

Therefore, the external harmful electromagnetic signals are preventedfrom undesirably affecting the chips 112 and 212 respectively mountedwithin the cavities 111 and 221 of the packages 100 and 200 and thuscausing deterioration of circuit functions and defective operations of adevice.

According to the embodiment of FIGS. 2A and 2 b, when the ceramicsubstrate 110 on which the conductive shielding layer 120 is provided iselectrically mounted on the main board 101, the conductive shieldinglayer 120 conveniently forms a circuit with the ground terminal of themain board 101. Likewise, according to the embodiment of FIGS. 4A and4B, when the ceramic substrate 210 on which the shielding substrate 220is stacked is electrically mounted on the main board 201, the shieldingsubstrate 220 conveniently forms a circuit with the ground terminal ofthe main board 201.

According to the present invention, a chip is disposed within a cavityof a ceramic substrate mounted on a main board. Then, a conductiveshielding layer is provided on the outside of the ceramic substrate, ora shielding substrate is integrally stacked on the ceramic substrate.Also, first and second ground lines electrically connected with the mainboard are provided in the ceramic substrate. Accordingly,electromagnetic signals generated during chip operation are preventedfrom undesirably affecting adjacent electronic components, or externalharmful electromagnetic waves are blocked. Thus, defective operations ofa device can be prevented, reliability of the package can be improved,and stable electrical characteristics can be achieved.

A package manufacturing process is simplified by conveniently performingthe following processes: a process of mounting a metal can for chipprotection on the ceramic substrate, a shielding process for protectingthe chip from the external environment without using the metal can, anda ground process of connecting the chip with the ground terminal of themain board. Also, manufacturing costs are lowered because of the reducednumber of components being used, miniaturization in device design can beachieved because of the small volume of the package, and the groundperformance can be improved.

While the present invention has been shown and described in connectionwith the exemplary embodiments, it will be apparent to those skilled inthe art that modifications and variations can be made without departingfrom the spirit and scope of the invention as defined by the appendedclaims.

1-9. (canceled)
 10. A semiconductor chip package comprising: a mainboard; a ceramic substrate having a cavity within which at least onechip is electrically mounted, the cavity being placed at a lower portionof the ceramic substrate facing the main board; and a conductiveshielding layer provided with a predetermined thickness on the outsideof the ceramic substrate, wherein the ceramic substrate comprises: atleast one first ground line electrically connecting the conductiveshielding layer with the main board; at least one second ground lineelectrically connecting the conductive shielding layer with the chip;and at least one signal line electrically connecting the chip with themain board, wherein the chip is mounted to the ceramic substrate bywire-bonding.
 11. A semiconductor chip package comprising: a main board;a ceramic substrate having a cavity within which at least one chip iselectrically mounted, the cavity being placed at a lower portion of theceramic substrate facing the main board; and a shielding substratestacked on the ceramic substrate and comprising a shielding layer,wherein the ceramic substrate comprises: at least one third ground lineelectrically connecting the shielding layer of the shielding substratewith the main board; at least one fourth ground line electricallyconnecting the shielding layer of the shielding substrate with the chip;and at least one signal line electrically connecting the chip with themain board.
 12. The semiconductor chip package of claim 11, wherein theshielding layer comprises: an upper conductive shielding layer providedat an upper portion of the shielding substrate; a lower conductiveshielding layer provided at a lower portion of the shielding substrate;and an intermediate conductive shielding layer disposed between theupper conductive shielding layer and the lower conductive shieldinglayer.
 13. The semiconductor chip package of claim 12, wherein the upperconductive shielding layer and the intermediate conductive shieldinglayer are connected through a conductive via, and the upper conductiveshielding layer and the lower conductive shielding layer are connectedthrough another conductive via.
 14. The semiconductor chip package ofclaim 12, wherein the upper conductive shielding layer covers theceramic substrate.
 15. The semiconductor chip package of claim 12,wherein the upper conductive shielding layer comprises bar-shapedpatterns alternately disposed on the ceramic substrate.
 16. Thesemiconductor chip package of claim 12, wherein the upper conductiveshielding layer comprises a helical pattern disposed on the ceramicsubstrate.
 17. The semiconductor chip package of claim 11, wherein thethird ground line comprises a third conductive via penetrating theceramic substrate and electrically connecting the shielding layer with aground terminal of the main board.
 18. The semiconductor chip package ofclaim 11, wherein the fourth ground line comprises a fourth conductivevia penetrating the ceramic substrate and electrically connecting theshielding layer with a ground terminal of the chip.
 19. Thesemiconductor chip package of claim 11, wherein the signal linecomprises: an inner pattern provided in the ceramic substrate andelectrically connected with a signal terminal of the chip; and a signalvia provided in the ceramic substrate and electrically connecting theinner pattern with a signal terminal of the main board.
 20. Thesemiconductor chip package of claim 11, wherein the cavity is filledwith a resin filler covering and protecting the chip.
 21. Thesemiconductor chip package of claim 11, wherein the chip is mounted tothe ceramic substrate by flip-chip bonding.
 22. The semiconductor chippackage of claim 11, wherein the chip is mounted to the ceramicsubstrate by wire-bonding.